Semiconductor device having device isolation region and portable electronic device

ABSTRACT

There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions are formed in one P-type semiconductor substrate. The N-type deep well regions are electrically isolated by the P-type semiconductor substrate. Over the N-type deep well regions, a P-type deep well region and a P-type shallow well region are formed to fabricate an N-type substrate variable-bias transistor. Over the N-type deep well region, an N-type shallow well region is formed to fabricate a P-type substrate variable-bias transistor. Further a P-type DTMOS and an N-type DTMOD are fabricated.

This application is the national phase under 35 U.S.C. § 371 of PCTInternational Application No. PCT/JP01/11228 which has an Internationalfiling date of Dec. 21, 2001, which designated the United States ofAmerica.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to semiconductor devices and portableelectronic device. More specifically, the invention relates to asemiconductor device using a dynamic threshold transistor and asubstrate bias-variable transistor, as well as a portable electronicdevice using this semiconductor device.

2. Background Art

In order to decrease power consumption in CMOS (Complementary MetalOxide Semiconductor) circuits using MOSFETs (Metal Oxide SemiconductorField Effect Transistors), it is most effective to lower the powersupply voltage. However, merely lowering the power supply voltage wouldcause the drive current of MOSFETs to lower, resulting in a loweroperating speed of the circuit. This phenomenon is known to becomenoticeable as the power supply voltage becomes a triple or less of thethreshold of the transistor. Although this phenomenon can be preventedby lowering the threshold, doing so would give rise to a problem ofincreases in off-leak current of MOSFETs. Therefore, the lower limit ofthe threshold is defined within a range over which the above problemdoes not occur. This in turn defines the limits of power consumptionreduction since the lower limit of the threshold corresponds to thelower limit of the power supply voltage.

Conventionally, there has been proposed a dynamic-threshold transistor(hereinafter, referred to as DTMOS) which performs dynamic-thresholdoperations and which employs a bulk substrate for alleviation of theabove-mentioned problem (Japanese Patent Laid-Open Publications HEI10-22462, Novel Bulk Dynamic Threshold Voltage MOSFET (B-DTMOS) withAdvanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C)Processes for Ultra Low Power Dual Gate CMOS, H. Kotaki et al., IEDMTech. Dig., p. 459, 1996). The aforementioned DTMOS has a characteristicof a capability of obtaining high drive current with low power supplyvoltage by virtue of its effective threshold lowering in an ON state.The reason why the effective threshold of a DTMOS lowers in the ON stateis that the gate electrode and the well region are electricallyshort-circuited.

The principle of operation of the N-type DTMOS is explained below. It isnoted that the P-type DTMOS operates similarly with the polarityreversed. In the N-type DTMOS, when the gate electrode voltage is at alow level (in an OFF state), the P-type well region voltage is also at alow level, the effective threshold has no differences from normalMOSFETs. Therefore, the off current value (off-leak) is the same as inthe case of normal MOSFETs.

On the other hand, when the gate electrode voltage is at a high level(in an ON state), the P-type well region voltage is also at a highlevel, and the effective threshold lowers by the substrate bias effect,so that the drive current increases compared with those of normalMOSFETs. Therefore, large drive current can be obtained with low powersupply voltage while low leak current is maintained.

In a DTMOS, the gate electrode and the well region are electricallyshort-circuited. Therefore, as the gate electrode voltage changes, thewell voltage also changes similarly. This accordingly requires the wellregion of each DTMOS to be mutually electrically isolated from the wellregions of its neighboring MOSFETs. For this reason, the well region ismade up of a shallow well region and a deep well region which aredifferent in conductive type from each other. Furthermore, the shallowwell regions of the respective DTMOSs are electrically isolated from oneanother by a device isolation region.

As a conventional method for suppressing off-leaks in low voltage driveand still obtaining high drive current, there has been a method in whichthe well-bias voltage is changed between standby and active states(Japanese Patent Laid-Open Publications HEI 6-216346 and 10-340998).

Hereinafter, a MOSFET in which the well bias is changed between standbyand active states will be referred to as substrate bias-variabletransistor.

The principle of operation of the N-type substrate bias-variabletransistor is explained below. It is noted that the P-type substratebias-variable transistor operates similarly with the polarity reversed.In an N-type substrate bias-variable transistor, when the circuit is inan active state, a 0 V or positive voltage (with a source voltagereferenced) is applied from a bias generation circuit to the P-type wellregion. With a positive voltage applied to the P-type well region, theeffective threshold lowers due to a substrate bias effect, and the drivecurrent increases as compared with the case of normal MOSFETs. When thecircuit is in a standby state, on the other hand, a negative voltage isapplied from the bias generation circuit to the P-type well region. As aresult of this, the effective threshold increases due to the substratebias effect, and the off-leak decreases as compared with normal MOSFETsor DTMOSs.

Generally, in a circuit using substrate bias-variable transistors,whether the active state or the standby state is effectuated is selectedfrom circuit block to circuit block. This is because providing the biasgeneration circuit for each device causes the number of devices and thecircuit area to increase considerably. From these reasons, the P-typewell region of an N-type MOSFET is common within a circuit block (thecase is the same with the N-type well region of a P-type MOSFET).Accordingly, in a circuit block which is in an active state, a 0 V orpositive voltage is applied to the well regions of all the N-typeMOSFETs, so that the off-leak increases as compared with normal MOSFETsor DTMOSs (the case is the same also with the P-type MOSFETs).

In the circuit using substrate bias-variable transistors, MOSFETs withina circuit block have to share a well region. For this purpose, the depthof the bottom face of the device isolation region is set deeper than thedepth of the junction between the source regions and drain regions ofthe MOSFETs and their shallow well region and, at the same time,shallower than the depth of the lower end of the shallow well region.

There has been disclosed a technique in which the DTMOS and thesubstrate bias-variable transistor are combined together to make thebest of their respective advantages (Japanese Patent Laid-OpenPublication HEI 10-340998).

FIG. 10 shows a cross-sectional view of a device fabricated by thistechnique. Referring to FIG. 10, there are shown, with referencenumerals having the following denotations, a P-type semiconductorsubstrate 11, an N-type deep well region 12, a P-type deep well region13, an N-type shallow well region 14, a P-type shallow well region 15, adevice isolation region 16, an N-type MOSFET source region 17, an N-typeMOSFET drain region 18, a P-type MOSFET source region 19, a P-typeMOSFET drain region 20, an N⁺ diffusion layer 21 for providing contactwith an N-type shallow well region, a P⁺ diffusion layer 22 forproviding contact with a P-type shallow well region, a gate insulator23, a gate electrode 24, a P-type substrate bias-variable transistor 25,an N-type substrate bias-variable transistor 26, an N-type DTMOS 27, aP-type DTMOS 28, a well-bias input terminal 29 for the P-type substratebias-variable transistor, a well-bias input terminal 30 for the N-typesubstrate bias-variable transistor, and a fixed bias input terminal 31for the P-type deep well region. In addition, although not shown, thegate electrode 24 and the P-type shallow well region 15 are electricallyshort-circuited in the N-type DTMOS 27, and the gate electrode 24 andthe N-type shallow well region 14 are electrically short-circuited inthe P-type DTMOS 28.

In the DTMOSs 27 and 28, the voltages of the shallow well regions 14 and15 change according to the voltage of the gate electrode 24. In order toprevent changes of the voltages of the shallow well regions 14 and 15from affecting shallow well regions of other devices, deep well regions13 and 12 opposite in conductive type to the shallow well regions 14 and15 are formed under those shallow well regions 14 and 15. Moreover, adevice isolation region 16 is formed at enough depth to electricallyisolate shallow well regions 14 and 15 of mutually neighboring devices.By doing so, the shallow well regions 14 and 15 are electricallyisolated from shallow well regions 14 and 15 of neighboring devices.Meanwhile, shallow well regions 14, 15 of the substrate bias-variabletransistors 25, 26 contained in one circuit block have to be provided incommon. Therefore, under the P-type shallow well regions 15 of theN-type substrate bias-variable transistors 26 in FIG. 10, is formed theP-type deep well region 13, which is integrated with a P-type shallowwell region 15 to form a common well region. To this P-type common wellregion, a voltage that differs between active and standby states isgiven via the well-bias input 30 for the N-type substrate bias-variabletransistor 26. In order to prevent any effects on devices of othercircuit blocks or DTMOS portion, the N-type deep well region 12 isformed further deeper in the substrate, by which the P-type deep wellregion 13 is electrically isolated.

Under the N-type shallow well region 14 of the P-type substratebias-variable transistor 25 in FIG. 10, is formed the N-type deep wellregion 12, which is integrated with the N-type shallow well region 14 toform a common well region. To this N-type common well region, a voltagethat differs between active and standby states is given via thewell-bias input terminal 29 for the P-type substrate bias-variabletransistor 25.

FIGS. 11 and 12 show the procedure of forming the deep well regions ofthis prior-art semiconductor device. As shown in FIG. 11, withphotoresist 33 used as a mask, dopant injection for forming the P-typedeep well region 13 is performed, and then dopant injection for formingan N-type deep well region 12 a further deeper is performed. Next, asshown in FIG. 12, with photoresist 34 used as a mask, dopant injectionfor forming an N-type deep well region 12 b is performed. In this case,the depth of the N-type deep well region 12 b is set to a level similarto the depth of the P-type deep well region 13. By these steps, theN-type deep well regions 12 a and 12 b are integrated together, by whichthe P-type deep well region 13 is electrically isolated.

In this way, the substrate bias-variable transistors 25, 26 and theDTMOSs 27, 28 are formed on the same substrate 11, making it possible torealize a circuit making the best of their respective advantages.

In the conventional semiconductor device, shown in FIG. 10, in which theDTMOSs 27, 28 and the substrate bias-variable transistors 25, 26 arecombined together, although the P-type deep well regions 13 can beelectrically isolated, the N-type deep well region 12 is common withinone substrate 11. Therefore, although the circuit block of the N-typesubstrate bias-variable transistors 26, 26 can be formed plurally withinthe same substrate 11, the circuit block of the P-type substratebias-variable transistor 25, 25 cannot be formed plurally, so that aplurality of circuit blocks cannot be divided properly into circuitblocks of the active state and circuit blocks of the standby state. Forexample, even when only part of the P-type gsubstrate bias-variabletransistors 25, 25 need to be put into active state, the entirety of theP-type substrate bias-variable transistors 25, 25 would come into anactive state, causing the leak current to increase. As a result, thepower consumption would increase.

SUMMARY OF THE INVENTION

The present invention having been accomplished with a view to solvingthese and other problems, it is therefore an object of the invention toreduce the power consumption of a semiconductor device, as well as aportable electronic device, using DTMOSs and substrate bias-variabletransistors.

According to the present invention, there is provided a semiconductordevice comprising:

a first-conductive-type semiconductor substrate;

a plurality of second-conductive-type deep well regions formed in thesemiconductor substrate;

a first-conductive-type deep well region formed in thesecond-conductive-type deep well regions;

a first first-conductive-type shallow well region formed on thefirst-conductive-type deep well region;

a first second-conductive-type shallow well region formed on thefirst-conductive-type deep well region;

a second first-conductive-type shallow well region formed on thesecond-conductive-type deep well regions;

a second second-conductive-type shallow well region formed on thesecond-conductive-type deep well regions;

a device isolation region;

a second-conductive-type field effect transistor formed on the firstfirst-conductive-type shallow well region;

an input terminal which is formed on the first first-conductive-typeshallow well region and which serves for changing a substrate bias ofthe second-conductive-type field effect transistor;

a first-conductive-type field effect transistor formed on the secondsecond-conductive-type shallow well region;

an input terminal which is formed on the second second-conductive-typeshallow well region and which serves for changing a substrate bias ofthe first-conductive-type field effect transistor;

a second-conductive-type dynamic threshold transistor which is formed onthe second first-conductive-type shallow well region and in which a gateelectrode and the second first-conductive-type shallow well region areelectrically connected to each other; and

a first-conductive-type dynamic threshold transistor which is formed onthe first second-conductive-type shallow well region and in which a gateelectrode and the first second-conductive-type shallow well region areelectrically connected to each other, wherein

the second first-conductive-type shallow well region is electricallyisolated from device to device by the device isolation region and thesecond-conductive-type deep well regions, and

the first second-conductive-type shallow well region is isolated fromdevice to device by the device isolation region and thefirst-conductive-type deep well region.

By virtue of the formation of the plurality of second-conductive-typedeep well regions as shown above, it becomes implementable to form, onone substrate, not only a plurality of circuit blocks ofsecond-conductive-type substrate-bias field effect transistors(substrate bias-variable transistors), as has been in the prior art, butalso a plurality of circuit blocks of first-conductive-typesubstrate-bias field effect transistors. Therefore, with respect to eachof the circuit blocks of first-conductive-type substrate-bias fieldeffect transistors and the circuit blocks of second-conductive-typesubstrate-bias field effect transistors, it becomes possible to properlydivide the circuit blocks into circuit blocks that should be put intothe active state and circuit blocks that should be put into the standbystate, so that the power consumption of the semiconductor device can bereduced.

Herein, the terms, “first conductive type”, refer to P-type or N-type.The terms, “second conductive type”, refer to N-type when the firstconductive type is P-type, or to P-type when the first conductive typeis N-type.

In one embodiment, the plurality of second-conductive-type deep wellregions are electrically isolated by the first-conductive-typesemiconductor substrate.

In this embodiment, since the plurality of second-conductive-type deepwell regions are electrically isolated by the first-conductive-typesemiconductor substrate, the plurality of second-conductive-type deepwell regions are electrically isolated with simplicity and low cost.

In one embodiment, a first-conductive-type dopant region is formedbetween the plurality of second-conductive-type deep well regions, andthe plurality of second-conductive-type deep well regions areelectrically isolated by the first-conductive-type semiconductorsubstrate and the first-conductive-type dopant region.

In this embodiment, since the first-conductive-type dopant region ispresent between the plurality of second-conductive-type deep wellregions, punch-throughs between the plurality of second-conductive-typedeep well regions are suppressed. Therefore, the margin between theplurality of second-conductive-type deep well regions is diminished,allowing the degree of integration to be improved.

In one embodiment, a device isolation region is formed between theplurality of second-conductive-type deep well regions, and the pluralityof second-conductive-type deep well regions are electrically isolated bythe first-conductive-type semiconductor substrate and the deviceisolation region.

In this embodiment, since the device isolation region is present betweenthe plurality of second-conductive-type deep well regions, parasiticcapacitance between the well regions (and silicon substrate) and gatelines or metal lines can be reduced.

In one embodiment, a first-conductive-type dopant region and a deviceisolation region are formed between the plurality ofsecond-conductive-type deep well regions, and the plurality ofsecond-conductive-type deep well regions are electrically isolated bythe first-conductive-type semiconductor substrate, thefirst-conductive-type dopant region and the device isolation region.

According to this embodiment, since the first-conductive-type dopantregion and the device isolation region are present between the pluralityof second-conductive-type deep well regions, the margin between thesecond-conductive-type deep well regions can be diminished, and theparasitic capacitance between the well regions (and silicon substrate)and gate lines or metal lines can be reduced.

In one embodiment, the plurality of second-conductive-type deep wellregions are electrically isolated at a boundary between thefirst-conductive-type field effect transistor and thesecond-conductive-type field effect transistor, at a boundary betweenthe first-conductive-type field effect transistor and thefirst-conductive-type dynamic threshold transistor, or at a boundarybetween the first-conductive-type field effect transistor and thesecond-conductive-type dynamic threshold transistor.

According to this embodiment, the plurality of second-conductive-typedeep well regions are electrically isolated at boundaries between thesecond-conductive-type deep well regions in circuit blocks of thefirst-conductive-type field effect transistors (substrate bias-variabletransistors) and the second-conductive-type deep well regions in otherdevice portions (circuit blocks of second-conductive-type substratebias-variable transistors, and first-conductive-type dynamic thresholdtransistors, and second-conductive-type dynamic threshold transistors).

Therefore, it becomes implementable not only to form, on one substrate,a plurality of circuit blocks of first-conductive-type substratebias-variable transistors as well as a plurality of circuit blocks ofsecond-conductive-type substrate bias-variable transistors, but also toreduce the junction capacitance between the second-conductive-type deepwell regions and the other well regions. Besides, it becomes achievableto suppress the latch-up phenomenon.

In one embodiment, out of the device isolation regions, given a width Aof either a device isolation region of which a shallow well regionplaced on one side and a shallow well region placed on the other sideare different in conductive type from each other, or a device isolationregion of which a deep well region placed on one side and a deep wellregion placed on the other side are different in conductive type fromeach other and moreover which is in contact with the deep well regionsplaced on both sides thereof, and given a width B of a device isolationregion of which a shallow well region placed on one side and a shallowwell region placed on the other side are identical in conductive type toeach other and of which a deep well region placed on one side and a deepwell region placed on the other side are identical in conductive type toeach other and which is in contact with the deep well regions placed onboth sides thereof, then A>B.

According to this embodiment, punch-throughs between well regions andthreshold shifts of devices due to dopant diffusion can be suppressed.

In one embodiment, out of the device isolation regions, given a width Aof either a device isolation region of which a shallow well regionplaced on one side and a shallow well region placed on the other sideare different in conductive type from each other, or a device isolationregion of which a deep well region placed on one side and a deep wellregion placed on the other side are different in conductive type fromeach other and moreover which is in contact with the deep well regionsplaced on both sides thereof, then 0.18 μm<A<0.7 μm.

According to this embodiment, punch-throughs between well regions andthreshold shifts of devices due to dopant diffusion can be suppressed.

In one embodiment, the device isolation regions are formed of STI(Shallow Trench Isolation).

According to this embodiment, since the device isolation regions areformed of STI, it becomes implementable to easily form device isolationregions of various widths, so that the semiconductor device can bemanufactured with simplicity and low cost.

In one embodiment, a complementary circuit is made up by thefirst-conductive-type dynamic threshold transistor and thesecond-conductive-type dynamic threshold transistor, or by thefirst-conductive-type field effect transistor and thesecond-conductive-type field effect transistor, or by thefirst-conductive-type dynamic threshold transistor and thesecond-conductive-type field effect transistor, or by thefirst-conductive-type field effect transistor and thesecond-conductive-type dynamic threshold transistor.

According to this embodiment, since the complementary circuit is madeup, the power consumption can even further be reduced.

The portable electronic device according to one embodiment includes thesemiconductor device.

This portable electronic device, by virtue of its including thesemiconductor device as described above, is reduced in the powerconsumption of LSI (Large-Scale Integrated Circuit) parts or the like toa large extent, thus capable of prolonging the battery life to a largeextent.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a semiconductor device of Embodiment 1 ofthe present invention;

FIG. 2 is a sectional view showing a semiconductor device of Embodiment2 of the invention;

FIG. 3 is a sectional view showing a semiconductor device of Embodiment3 of the invention;

FIG. 4 is a sectional view showing a semiconductor device of Embodiment4 of the invention;

FIG. 5 is a sectional view showing the semiconductor device ofEmbodiment 4 of the invention;

FIG. 6 is a plan view schematically showing the semiconductor device ofEmbodiment 4 of the invention;

FIG. 7 is a view showing the method of fabricating deep well regions ofthe semiconductor device of Embodiment 4;

FIG. 8 is a view showing the method of fabricating deep well regions ofthe semiconductor device of Embodiment 4;

FIG. 9 is a block diagram showing a portable electronic device of thepresent invention;

FIG. 10 is a sectional view of a conventional semiconductor device;

FIG. 11 is a view showing the method of fabricating deep well regions ofthe conventional semiconductor device;

FIG. 12 is a view showing the method of fabricating deep well regions ofthe conventional semiconductor device.

DESCRIPTION OF THE INVENTION

Hereinbelow, the present invention is described in detail by way ofembodiments thereof illustrated in the accompanying drawings.

Semiconductor substrates to be used for the present invention, althoughnot particularly limited, are preferably silicon substrates. Thesemiconductor substrate may have either conductive type, P-type orN-type. It is noted that the following embodiments show a case where aP-type semiconductor substrate is used. In the case where an N-typesemiconductor substrate is used, reversing the conductive type of allthe injected dopants given hereinbelow allows a semiconductor device ofsimilar functions to be fabricated.

EMBODIMENT 1

Embodiment 1 of the present invention is described with reference toFIG. 1. FIG. 1 is a sectional view of a semiconductor device ofEmbodiment 1 of the invention. In FIG. 1, gate insulator, gateelectrode, source region, drain region, interlayer insulator and uppermetal interconnects are omitted. Also, though the structure is omittedin FIG. 1, reference numerals 25, 26 represent substrate bias-variabletransistors having the same structure as that of the prior-art exampleshown in FIG. 10, and reference numerals 27, 28 represent DTMOSs havingthe same structure as that of the prior-art example shown in FIG. 10.Further, in FIG. 1, the same constituent parts as those of the prior-artexample shown in FIG. 10 are designated by the same reference numeralsas those of FIG. 10 and their description is omitted.

In the semiconductor device of FIG. 1, the N-type deep well region 12 inthe prior-art semiconductor device shown in FIG. 10 is electricallyparted at a region where no well dopant is injected (the portion ofP-type semiconductor substrate 11). The region where no well dopant isinjected can be formed by masking there with photoresist in the processof well dopant injection.

Next, the procedure for fabricating the semiconductor device shown inFIG. 1 is described. Device isolation regions 16 are formed on thesemiconductor substrate 11. The device isolation regions 16 can beformed by using, for example, STI process. However, the method forforming the device isolation regions 16, not being limited to the STIprocess, needs only to have a function that the device isolation regions16 electrically isolate the shallow well region. For example, thesubstance to be filled in the device isolation regions may be not onlysilicon oxide or silicon nitride but also electrically conductivesubstances such as polysilicon or amorphous silicon. However, whenelectrically conductive substance such as polysilicon or amorphoussilicon is buried, it is necessary to ensure non-conductivity of thedevice isolation regions by, for example, preliminarily oxidizing sidewalls of the device isolation regions 16.

The depth of the device isolation regions 16 is set to such a level thatshallow well regions of mutually neighboring devices are electricallyisolated and that their deep well regions are not electrically isolated.The depth of the device isolation regions 16 is preferably, 0.2 to 2 μm,for example.

Next, a plurality of N-type deep well regions 12, 12 are formed on thesemiconductor substrate 11. The difference from the procedure of theprior-art example is that places where the N-type deep well regions 12,12 are parted from each other are masked with photoresist so that dopantinjection is not applied thereto. Conditions of dopant injection may bethe same as those will be described later in Embodiment 4.

In addition, although the N-type deep well regions 12, 12 areelectrically parted from each other by the semiconductor substrate(P-type in conductive type) 11, yet a low dopant level (about 10¹⁵ cm⁻³)of the semiconductor substrate 11 has a need for providing enoughpartition width for prevention of occurrence of punch-throughs betweenthe N-type deep well regions 12, 12.

Next, P-type deep well regions 13, 13 are formed on the N-type deep wellregions 12, 12, respectively. Conditions of dopant injection may be thesame as those will be described later in Embodiment 4. Two P-type deepwell regions 13, 13 on each one N-type deep well region 12 areelectrically parted from each other by a shallow portion of the N-typedeep well region 12. Further, a first N-type shallow well region 14 isformed on the P-type deep well region 13, and moreover a second N-typeshallow well region 14 is formed on the N-type deep well region 12. Anexample of dopant ions that give the N-type conductivity is ³¹P⁺. Forexample, when ³¹P⁺ is used as dopant ions, the well region can be formedunder the conditions of an injection energy of 130 to 900 keV and aninjection quantity of 5×10¹¹ to 1×10¹⁴ cm⁻².

Next, a first P-type shallow well region 15 is formed on the P-type deepwell region 13, and moreover a second P-type shallow well region 15 isformed on the N-type deep well region 12. An example of dopant ions thatgive the P-type conductivity is ¹¹B⁺. For example, when ¹¹B⁺ ions areused as dopant ions, the well region can be formed under the conditionsof an injection energy of 60 to 500 keV and an injection quantity of5×10¹¹ to 1×10¹⁴ cm⁻².

The order of dopant injection for forming the well regions is notlimited to the above-described one, and may be changed.

It is noted that the depth of the junction between the shallow wellregions 14, 15 and the deep well regions 12, 13 as well as the depth ofthe junction between the N-type deep well region 12 and the P-type deepwell region 13 are determined according to the injection conditions forthe shallow well regions 14, 15, the injection conditions for the deepwell regions 12, 13 and the thermal processes to be performedafterwards. The depth of the device isolation regions 16 is set to sucha level that the shallow well regions 14, 15 of neighboring devices areelectrically isolated and that their deep well regions 12, 13 are notelectrically isolated.

Furthermore, for reduction of resistance of the shallow well regions 14,15, heavily doped buried regions of the same conductive type as thedopant ions of the shallow well regions 14, 15 may be formed in theshallow well regions 14, 15. Reduced resistance of the shallow wellregions 14, 15 allows an input to the gate electrode to be promptlypropagated to the shallow well regions 14, 15, making it possible toobtain the full substrate bias effect so that higher-speed operations ofthe DTMOSs 27, 28 can be implemented. The heavily doped buried regionscan be formed under the conditions of, for example, dopant ions of ¹¹B⁺,an injection energy of 100 to 400 keV and an injection quantity of1×10¹² to 1×10¹⁴ cm⁻² for the formation in the P-type shallow wellregion, or conditions of dopant ions of ³¹P⁺, an injection energy of 240to 750 keV and an injection quantity of 1×10¹² to 1×10¹⁴ cm⁻² for theformation in the N-type shallow well region.

Further, in order to prevent the dopant level from being excessivelylightened in the substrate surface region, dopant ions of the sameconductive type as the dopant ions of the shallow well regions 14, 15may also be injected as a punch-through stopper injection into theshallow well regions 14, 15. The punch-through stopper injection can becarried out, for example, under the conditions of dopant ions of ¹¹B⁺,an injection energy of 10 to 60 keV and an injection quantity of 5×10¹¹to 1×10¹³ cm⁻² for the formation in the P-type shallow well region 15,or conditions of dopant ions of ³¹P⁺, an injection energy of 30 to 150keV and an injection quantity of 5×10¹¹ to 1×10¹³ cm⁻² for the formationin the N-type shallow well region 14.

Next, although not shown, a gate insulator and a gate electrode (see thegate insulator 23 and the gate electrode 24 of the prior-art exampleshown in FIG. 10) are formed in this order.

Material of the gate insulator is not particularly limited as far as ithas insulation property. When a silicon substrate 11 is used as in thisEmbodiment 1, silicon oxide, silicon nitride or a laminate of those maybe used for the gate insulator. Further, high-permittivity films ofaluminum oxide, titanium oxide, tantalum oxide or the like or theirlaminates may also be used. Preferably, the gate insulator has athickness of 1 to 10 nm in the case where silicon oxide is used. Thegate insulator can be formed by CVD (Chemical Vapor Deposition) process,sputtering process, thermal oxidation or other like process.

Next, material of the gate electrode is not particularly limited as faras it has electrical conductivity. When a silicon substrate is used,silicon films of polysilicon, single crystal silicon or the like may bementioned as examples. Further, in addition to these, metal films ofaluminum, copper or the like are available. Preferably, the gateelectrode has a thickness of 0.1 to 0.4 μm. The gate electrode can beformed by CVD process, evaporation process or other like process.

Further, a side wall spacer may be formed on the side wall of the gateelectrode. Material of this side wall spacer is not particularly limitedas far as it is an insulating film, and exemplified by silicon oxide,silicon nitride and the like.

Next, although not shown, a gate-substrate connection region is formedat portions that are to form the DTMOSs. In regions other than thesource regions, the drain regions and the channel regions, for theformation of a gate-substrate connection region for electricallyconnecting the gate electrode and the shallow well regions to eachother, the gate electrode and the gate oxide are partly etched until theground substrate is exposed. In this exposed region, a heavily dopedregion (P-type heavily doped region in NMOS, and N-type heavily dopedregion in PMOS) is formed. In a silicification step to be performedlater, the gate electrode and the shallow well regions are electricallyconnected to each other in the gate-substrate connection region.

Next, although not shown, source regions and drain regions of aconductive type opposite to the conductive type of the shallow wellregions 14, 15 are formed on the surface layer of the shallow wellregions 14, 15.

The source regions and the drain regions can be formed in self-alignmentfashion, for example, by injecting dopant ions of a conductive typeopposite to the conductive type of the shallow well regions with thegate electrode used as a mask. The source regions and the drain regionscan be formed, for example, under the conditions of an injection energyof 3 to 100 keV and an injection quantity of 1×10¹⁵ to 1×10¹⁶ cm⁻² forthe case where ⁷⁵As⁺ ions are used as dopant ions, or conditions of aninjection energy of 1 to 20 keV and an injection quantity of 1×10¹⁵ to1×10¹⁶ cm⁻² for the case where ¹¹B⁺ ions are used as dopant ions. It isnoted that the surface layers of the shallow well regions under the gateelectrode function as channel regions.

Further, the source regions and the drain regions may have an LDD(Lightly Doped Drain) region on their gate electrode side. The LDDregion can be formed in self-alignment fashion, for example, byinjecting dopant ions of a conductive type opposite to the conductivetype of the shallow well regions with the gate electrode used as a mask.In this case, the source regions and the drain regions can be formed inself-alignment fashion by, after the formation of the LDD region,forming the side wall spacer on the side wall of the gate electrode andinjecting ions with the gate electrode and the side wall spacer used asmasks. The dopant ion injection for forming the LDD region can beimplemented, for example, under the conditions of an injection energy of3 to 100 keV and an injection quantity of 5×10¹³ to 1×10¹⁵ cm⁻² for thecase where ⁷⁵As⁺ ions are used as dopant ions, or conditions of aninjection energy of 1 to 20 keV and an injection quantity of 1×10¹³ to5×10¹⁴ cm⁻² for the case where ¹¹B⁺ ions are used as dopant ions.

In addition, as the dopant ions for forming the source regions, thedrain regions and the LDD region, it is also possible to use ³¹P⁺ ions,¹²²Sb⁺ ions, ¹⁵In⁺ ions, ⁴⁹BF₂ ⁺ ions or the like, in addition to theabove-mentioned ¹¹B⁺ ions and ⁷⁵As⁺ ions.

Further, the source regions, the drain regions and the gate electrodehave their surface layers silicified with a view to lowering theirrespective resistances and improving their electrical conductivitieswith their respective connecting lines. By this silicification, the gateelectrode and the shallow well regions are electrically connected toeach other in the gate-substrate connection region. The silicide may begiven by, for example, tungsten silicide, titanium silicide, or thelike.

In addition, the source regions and the drain regions may also beprovided in a stacking type (see Japanese Patent Laid-Open Publication2000-82815). In this case, the source regions and the drain regions canbe made smaller in area, allowing higher integration to be achieved.

After that, an activation annealing for the dopants is performed. Theactivation annealing is carried out under such conditions that thedopants are fully activated and moreover prevented from beingexcessively diffused. For example, in the case where the N-type dopantis ⁷⁵As⁺ and the P-type dopant is ¹¹B⁺, it is appropriate that after theinjection of ⁷⁵As⁺, an annealing is done at 800 to 1000° C. for about 10to 100 minutes and subsequently, after the injection of ¹¹B⁺, anannealing is done at 800 to 1000° C. for 10 to 100 seconds. In addition,in order to obtain a gentler dopant profile for the shallow well regionsand the deep well regions, another annealing may be performed beforeinjecting dopants for the source regions and the drain regions.

After that, interconnecting lines and the like are formed by knowntechniques, and thus the semiconductor device can be formed.

Although the above description has been made on a case where only thesubstrate bias-variable transistors 25, 26 and the DTMOSs 27, 28 areformed for explanation's sake, it is also possible that normal MOSFETsare mixed therein. Otherwise, DTMOSs and normal MOSFETs only are alsopossible. In this case, the voltage for the shallow well regions mayappropriately be fixed for devices that are to be formed into normalMOSFETs.

Thus, in the semiconductor device of this Embodiment 1, it becomesimplementable to form, on one substrate 11, not only a plurality ofcircuit blocks of N-type substrate bias-variable transistors 26, 26 butalso a plurality of circuit blocks of P-type substrate bias-variabletransistors 25, 25. Therefore, with respect to the individual N-type andP-type circuit blocks, it becomes possible to properly divide thecircuit blocks into circuit blocks that should be put into the activestate and circuit blocks that should be put into the standby state, sothat the power consumption of the semiconductor device can be reduced.

In the above-described Embodiment 1, a P-type semiconductor substrate 11has been used. However, even when an N-type semiconductor substrate isused with the conductive type of each well region reversed to theforegoing, the absolutely same functions and effects can be obtained.

EMBODIMENT 2

Embodiment 2 of the present invention is described with reference toFIG. 2. FIG. 2 is a sectional view of a semiconductor device accordingto Embodiment 2 of the invention. In this FIG. 2, gate insulator, gateelectrode, source region, drain region, interlayer insulator and uppermetal interconnects are omitted. Also, in FIG. 2, the same constituentparts as those shown in FIG. 1 are designated by the same referencenumerals as those of FIG. 1 and their description is omitted.

The semiconductor device of Embodiment 2 differs from the semiconductordevice of Embodiment 1 in that a P-type dopant region 35 is provided ata place where the N-type deep well regions 12, 12 are parted from eachother. The dopant level of this P-type dopant region 35 is higher thanthe dopant level of the P-type substrate 11 so that punch-throughsbetween the N-type deep well regions 12, 12 can effectively besuppressed. Therefore, the margin for electrical isolation between theN-type deep well regions 12, 12 can be reduced.

Next, the procedure for fabricating the semiconductor device shown inFIG. 2 is described. The procedure for fabricating the semiconductordevice of this Embodiment 2 differs from the procedure for fabricatingthe semiconductor device of Embodiment 1 only in that a step for formingthe P-type dopant region 35 is added.

The P-type dopant region 35, which is intended for isolation of theN-type deep well regions 12, 12, preferably has a depth generallysimilar to that of the N-type deep well regions 12. For this purpose, itis preferable to increase one more photomask for forming the P-typedopant region 35.

The dopant injection for forming the P-type dopant region 35 can beformed under the conditions of an injection energy of 100 to 1500 keVand an injection quantity of 5×10¹¹ to 1×10¹⁴ cm⁻², for example, with¹¹B⁺ ions used as the dopant ions.

In addition, in the formation of the P-type dopant region 35, it ispreferable to perform a shallow dopant injection subsequent to theforegoing dopant injection (i.e., a two-step injection) for obtainmentof enough dopant level at regions near the substrate surface. Thisshallow well injection can be formed under the conditions of aninjection energy of 60 to 500 keV and an injection quantity of 5×10¹¹ to1×10 ¹⁴ cm⁻² for example, with ¹¹B⁺ ions used as the dopant ions. Thedopant injection step for the P-type shallow well region 15 may be usedalso for this shallow dopant injection. In this case, the dopantinjection process can be reduced by one step.

Thus, by the formation of the P-type dopant region 35, punch-throughsbetween the N-type deep well regions 12, 12 are suppressed. Accordingly,the margin between the N-type deep well regions 12, 12 is diminished,and the degree of integration can be improved, as compared with thesemiconductor device of Embodiment 1.

EMBODIMENT 3

Embodiment 3 of the present invention is described with reference toFIG. 3. FIG. 3 is a sectional view of a semiconductor device which is athird embodiment of the invention. In FIG. 3, gate insulator, gateelectrode, source region, drain region, interlayer insulator and uppermetal interconnects are omitted. Also, in FIG. 3, the same constituentparts as those shown in FIG. 2 are designated by the same referencenumerals as those of FIG. 2 and their detailed description is omitted.

The semiconductor device of this Embodiment 3 differs from thesemiconductor device of Embodiment 2 only in the following points.

Firstly, a device isolation region 161 having a width larger than thewidth of the foregoing device isolation region 16 is provided at placeswhere the P-type dopant region 35 is provided for prevention ofpunch-throughs and parting of the N-type deep well regions 12, 12. As aresult of this, parasitic capacitance between the well regions (siliconsubstrate) and gate lines or metal lines can be reduced. Further, it isno longer necessary to perform the shallow dopant injection that isperformed to form the P-type dopant region 35 in the semiconductordevice of Embodiment 2, and one time dopant injection suffices.

Secondly, a wide device isolation region 162 is provided also at placesother than the places where the P-type dopant region 35 is to be formed.The width of this device isolation region 162 is set as follows. Whenthe deep well regions 12, 13 differ in conductive type between the twosides of the device isolation region 162, for example, at the boundarybetween the N-type DTMOS 27 and the N-type substrate bias-variabletransistor 26, the deep well region 12 on the N-type DTMOS 27 side isN-type and the deep well regions 13, 12 on the N-type substratebias-variable transistor 26 side is of a P-type/N-type stackedstructure. Since the N-type deep well region 12, which is the deeperside of the P-type/N-type stacked structure, gives no influences interms of device isolation, it can be said that the deep well regions 12,13 are opposite in conductive type between the two sides of the deviceisolation region 162. In this case, there arises a problem ofpunch-through between the P-type shallow well region 15 of the N-typeDTMOS 27 and the P-type deep well region 13 of the N-type substratebias-variable transistor 26. Further, there is a possibility thatdopants contained in the N-type deep well regions 12 of the N-typeDTMOSs 27 may be diffused, causing the threshold of the N-type substratebias-variable transistors 26 to change. Another example is the boundarybetween the N-type DTMOS 27 and the P-type DTMOS 28, where similarproblems may occur. In this case, between the two sides of the deviceisolation region 162 placed at the boundary, the shallow well regions15, 14 are opposite in conductive type and moreover the deep wellregions 12 and 13 are also opposite in conductive type. Otherwise,although not shown, similar problems may occur further at the boundarybetween the P-type DTMOS and the P-type substrate bias-variabletransistor, the boundary between the P-type DTMOS and the N-typesubstrate bias-variable transistor, the boundary between the N-typeDTMOS and the P-type substrate bias-variable transistor, and theboundary between the N-type substrate bias-variable transistor and theP-type substrate bias-variable transistor. Therefore, when the shallowwell regions 14, 15 are opposite in conductive type between the twosides of the device isolation region 162, and when the deep well regions12, 13 are opposite in conductive type between the two sides of thedevice isolation region 162, and when the shallow well regions 12, 13are opposite in conductive type between the two sides of the deviceisolation region 162 and moreover the deep well regions 12, 13 are alsoopposite in conductive type, the width of the device isolation region162 needs to be wide to such an extent that neither the aforementionedpunch-through nor changes in threshold occur. For example, even if thedopant injection range for the deep well regions is set as shallow asabout 0.3 μm, the dopants would spread also laterally in injectionprocess, and moreover diffused further laterally due to subsequentthermal diffusion. Even under the injection conditions described above,it was impossible to suppress changes in threshold when the width of thedevice isolation region was less than 0.18 μm. Also, with the width ofthe device isolation region not less than 0.7 μm, the margin requiredfor device isolation would be no longer negligible. Accordingly, forprevention of occurrence of the punch-through and changes in threshold,the width of the device isolation region 162 is preferably 0.18 μm to0.7 μm. Meanwhile, when the shallow well region 14 or 15 is identical inconductive type between the two sides of the device isolation region 16and moreover the deep well region 12 or 13 is also identical inconductive type (where the shallow well regions and the deep wellregions may be different in conductive type for each other), smallerwidths of the device isolation region 16 allow the margin to be reduced.Therefore, the width is normally set near machining limitations. In thiscase, the width of the device isolation region 16 may be set to, forexample, 0.05 to 0.35 μm.

In the semiconductor device of this Embodiment 3, since the wide deviceisolation region 161 is provided on the P-type dopant region 35 servingfor isolating the N-type deep well regions 12, 12 from each other,parasitic capacitance can be reduced. Therefore, higher-speed circuitsor lower power consumption can be achieved. Also, the dopant injectionprocess in forming the P-type dopant region 35 can be simplified. Thus,the manufacturing cost can be reduced.

EMBODIMENT 4

The semiconductor devices of Embodiments 1 to 3 have problems asdescribed below.

In the semiconductor devices of Embodiment 1 to 3, the N-type deep wellregion 12 in a circuit block of P-type substrate bias-variabletransistors 25, 25 is integrated with the N-type deep well region 12 ina circuit block of N-type substrate bias-variable transistors 26 and ina circuit block of DTMOSs 27, 28. Therefore, changing over betweenactive and standby states in a circuit block of the P-type substratebias-variable transistors 25, 25 causes the bias of the whole N-typedeep well region 12 to change, which in turn causes large amounts ofcharges to be charged and discharged. As a result, the power consumptionincreases.

Furthermore, in the foregoing semiconductor devices of Embodiment 1 to3, putting the P-type substrate bias-variable transistors 25 into theactive state (i.e., giving a voltage lower than the power supply voltageto the N-type deep well regions 12) makes it more likely that a latch-upphenomenon is induced. In an NPNP structure having routes passingthrough the N-type shallow well region 14, the P-type deep well region13, the N-type deep well region 12 of the P-type DTMOS 28 and the P-typeshallow well region 15 of the N-type DTMOS 27, a case (undershoot) isdiscussed where a bias lower than ground voltage is applied to theN-type shallow well region 14 of the P-type DTMOS 28. In the DTMOSs 27,28, in which the gate electrode and the shallow well regions 15, 14 areelectrically connected to each other, it can occur that a bias not morethan the ground voltage is applied to the N-type shallow well region 14of the P-type DTMOS 28 through the gate electrode. In this case, aforward voltage is applied to the junction between the N-type shallowwell region 14 of the P-type DTMOS 28 and the P-type deep well region13, so that electrons are injected into the P-type deep well region 13.The electrons injected into the P-type deep well region 13 reach theN-type deep well region 12, causing the voltage of the N-type deep wellregion 12 to decrease. With the voltage of the N-type deep well region12 decreased, holes are injected from the P-type shallow well region 15of the N-type DTMOS 27 into the N-type deep well region 12. The holesinjected into the N-type deep well region 12 reach the P-type deep wellregion 13, causing the voltage of the P-type deep well region 13 toincrease. With the voltage of the P-type deep well region 13 increased,electrons injected from the N-type shallow well region 14 of the P-typeDTMOS 28 into the P-type deep well region 13 increase more and more.Through iterations of these process (with a positive feedback applied),an abnormal current flows in the NPNP structure, giving rise to alatch-up phenomenon. In this connection, if a voltage lower than thepower supply voltage has been applied to the N-type deep well region 12from the beginning (i.e., if the P-type substrate bias-variabletransistor 25 has been in an active state), the latch-up phenomenon ismore likely to occur. Further, also when the P-type substratebias-variable transistor 25 comes into a standby state (i.e., also whena voltage higher than the power supply voltage is applied to the N-typedeep well region 12), it become more likely that a latch-up phenomenonis induced. In this case, a large inverse-bias is applied to thejunction between the P-type shallow well region 15 and the N-type deepwell region 12 of the N-type DTMOS 27, as well as to the junctionbetween the P-type deep well region 13 and the N-type deep well region12. This causes a punch-through to occur between the P-type shallow wellregion 15 of the N-type DTMOS 27 and the P-type deep well region 13,triggering the occurrence of a latch-up phenomenon in the NPNPstructure. As to the route of the latch-up, in addition to theabove-mentioned one, such an NPNP structure may also be mentioned as oneincluding a route which passes the drain region of the N-type DTMOS 27,the P-type shallow well region 15 of the N-type DTMOS 27, the N-typedeep well region 12 and the P-type deep well region 13. Thus, largelychanging bias of the N-type deep well region 12 makes it difficult tocontrol the latch-up phenomenon. As a result, the device reliabilitydeteriorates.

Embodiment 4 of the present invention has solved the above-describedproblems, and is described with reference to FIGS. 4 to 8.

FIGS. 4 and 5 are sectional views showing a semiconductor device ofEmbodiment 4 of the invention. In FIGS. 4 and 5, interlayer insulatorand upper metal interconnects are omitted. FIG. 6 is a schematic view ofa plan.

First, the semiconductor device of this embodiment is explained withreference to FIG. 4. The semiconductor device shown in FIG. 4 differsfrom the semiconductor devices shown in FIGS. 1 to 3 in the followingpoints. That is, the N-type deep well region 12 in a circuit block ofP-type substrate bias-variable transistors 25, 25 is electricallyisolated from the N-type deep well region 12 in a circuit block ofN-type substrate bias-variable transistors 26, 26 and in a circuit blockof the DTMOS portion (a region including DTMOSs 27, 28). At a placewhere the N-type deep well regions 12, 12 are isolated, a deviceisolation region 165 is provided as depicted in FIG. 4. With thisprovision of the device isolation region 165 at a place where the N-typedeep well regions 12, 12 are isolated, the parasitic capacitance withthe gate lines or the upper metal interconnects can be decreased ascompared with the case where the device isolation region 165 is notprovided.

Preferably, the place where the N-type deep well regions 12, 12 areparted from each other is determined so that an input voltage from thewell-bias input terminal 29 to the P-type substrate bias-variabletransistor 25 ranges to neither the circuit block of N-type substratebias-variable transistors 26, 26 nor the DTMOS portion. That is, theplace where the N-type deep well regions 12, 12 are parted from eachother is, preferably, determined at the boundary between a circuit blockof P-type substrate bias-variable transistors 25 and a circuit block ofN-type substrate bias-variable transistors 26, or the boundary between acircuit block of N-type substrate bias-variable transistors 26 and theDTMOS portion. FIG. 5 shows a sectional view of the boundary between thecircuit block of P-type substrate bias-variable transistors 25 and theN-type DTMOS portion (a region including the N-type DTMOS 27). Theboundary between the circuit block of P-type substrate bias-variabletransistors 25 and the N-type DTMOS portion (a region including theN-type DTMOS 27) is similar to the case of the boundary between acircuit block portion of P-type substrate bias-variable transistors 25and a circuit block of N-type substrate bias-variable transistors 26.

Next, the semiconductor device of this Embodiment 4 is explained withreference to FIG. 6. It is noted that individual interconnects and biasgeneration circuits to make up the circuit are omitted in FIG. 6. On asemiconductor substrate is a region 51 over which a voltage-varyingN-type deep well region (an N-type deep well region connected to thewell-bias input terminal for the P-type substrate bias-variabletransistors) is formed. Further, on the semiconductor substrate is aregion 52 over which a voltage-fixed N-type deep well region is formed.Within the region 51 over which a voltage-varying N-type deep wellregion is formed, a block 53 composed of P-type substrate bias-variabletransistors is formed. Within the voltage-fixed N-type deep well region52, a block 54 composed of N-type substrate bias-variable transistors, ablock 55 composed of N-type DTMOSs, and a block 56 composed of P-typeDTMOSs are formed.

The block 53 composed of P-type substrate bias-variable transistors isconnected to another block 53 composed of P-type substrate bias-variabletransistors by an upper interconnect 57 that connects together commonwell regions of the substrate bias-variable transistors. The blocks 53,53 composed of P-type substrate bias-variable transistors and connectedto each other in this way form one circuit block (composed of P-typesubstrate bias-variable transistors). To the common well region of thiscircuit block, the power supply voltage or a voltage lower than thepower supply voltage is given in an active state and a voltage higherthan the power supply voltage is given in a standby state, from a biasgeneration circuit.

The block 54 composed of N-type substrate bias-variable transistors isconnected to another block 54 composed of N-type substrate bias-variabletransistors by an upper interconnect 57 that connects together commonwell regions of the N-type substrate bias-variable transistors. Theblocks 54, 54 composed of N-type substrate bias-variable transistors andconnected to each other in this way form one circuit block (composed ofN-type substrate bias-variable transistors). To the common well regionof this circuit block, a 0 V or positive voltage is given in an activestate and a negative voltage is given in a standby state, from a biasgeneration circuit.

With the use of the well structure shown in FIGS. 4 and 5 and furtherwith an arrangement shown in FIG. 6, a plurality of circuit blocks ofsubstrate bias-variable transistors can easily be formed in a circuit inwhich substrate bias-variable transistors and DTMOSs are mixedlycontained. Furthermore, complementary MOS (CMOS) circuits can be made upby connecting N-type devices and P-type devices with the upperinterconnects.

Next, the procedure for fabricating the semiconductor device shown inFIGS. 4 to 6 is described.

The procedure for fabricating the semiconductor device of thisEmbodiment 4 is the same as that for fabricating the semiconductordevice of Embodiment 1. A case of forming the deep well region of thesemiconductor device shown in FIG. 4 is explained with reference toFIGS. 7 and 8.

As shown in FIG. 7, with photoresist 33 used as a mask, the N-type deepwell region 12 a is formed on the semiconductor substrate 11. An exampleof dopant ions that give the N-type conductivity is ³¹P⁺. For example,when ³¹P⁺ is used as dopant ions, the well region can be formed underthe conditions of an injection energy of 500 to 3000 keV and aninjection quantity of 5×10¹¹ to 1×10¹⁴ cm⁻². Subsequently, with the samemask 33 used, the P-type deep well region 13 is formed at a positionshallower than the N-type deep well region 12 a. An example of dopantions that give the P-type conductivity is ¹¹B⁺. For example, when ¹¹B⁺ions are used as dopant ions, the well region can be formed under theconditions of an injection energy of 100 to 1000 keV and an injectionquantity of 5×10¹¹ to 1×10¹⁴ cm⁻².

Next, as shown in FIG. 8, with photoresist 34 used as a mask, the N-typedeep well region 12 b is formed. The depth of dopant injection for theN-type deep well region 12 b is preferably shallower than that of theN-type deep well region 12 a and generally equal to that of the P-typedeep well region 13. An example of dopant ions that give the N-typeconductivity is ³¹P⁺. For example, when ³¹P⁺ is used as dopant ions, thewell region can be formed under the conditions of an injection energy of240 to 1500 keV and an injection quantity of 5×10¹¹ to 1×10¹⁴ cm⁻². Theregion 12 a and the region 12 b are integrated together to form anN-type deep well region. Also, by parting the N-type deep well region 12b (masking with the photoresist 34 so that dopant injection is notapplied thereto), the N-type deep well regions can be electricallyisolated from each other.

It is noted that the N-type deep well regions 12 are electricallyisolated from each other by the semiconductor substrate (P-typeconductivity) 11. The semiconductor substrate 11, which is generally lowin dopant level (about 10¹⁵ cm⁻³), needs to have enough isolation widthin order to prevent the punch-throughs between the N-type deep wellregions 12, 12. For the prevention of punch-throughs between the N-typedeep well regions 12, 12, it is also allowable to inject a P-type dopantto between the N-type deep well regions 12, 12 with one more lithographyphotomask increased, as has been done in Embodiment 2 or Embodiment 3.

Although the above description has been made on a case where only thesubstrate bias-variable transistors 25, 26 and the DTMOSs 27, 28 areinvolved for explanation's sake, it is also possible that MOSFETs ofnormal structure are mixed. In this case, the voltage for the shallowwell regions may appropriately be fixed for devices that are to benormal MOSFETs.

As shown in FIGS. 4 and 5, in the above semiconductor device, theshallow well regions 15, 14 of the DTMOSs 27, 28 are electricallyisolated from device to device by the deep well regions 12, 13 ofopposite conductive types and the device isolation region 162. Also, thecommon well regions 12, 14 of P-type substrate bias-variable transistors25 are electrically isolated from circuit block to circuit block by thedevice isolation region 165 and the P-type semiconductor region 11.Furthermore, the common well regions 13, 15 of N-type substratebias-variable transistors 26 are electrically isolated from circuitblock to circuit block by the device isolation regions 162, 165 and theN-type deep well region 12.

Therefore, according to the semiconductor device of this Embodiment 4,any arbitrary number of circuit blocks of the substrate bias-variabletransistors 25, 26 can be formed for each conductive type. As a resultof this, it becomes implementable to properly divide the circuit blocksinto active-state circuit blocks and standby-state circuit blocks, thusmaking it possible to reduce the power consumption of the semiconductordevice.

Moreover, according to the semiconductor device of this Embodiment 4,the area of the PN junction between the common well regions 12, 14 and13, 15 of the substrate bias-variable transistors 25, 26 and theirneighboring well regions of the opposite conductive type can besuppressed to one approximately equally to the area of the circuit blockof the substrate bias-variable transistors 25, 26. Therefore, in thesemiconductor device of this Embodiment 4, quantities of charges anddischarges upon changes in the voltage of the common well regions of thesubstrate bias-variable transistors 25, 26 are reduced. As a result ofthis, the power consumption of the semiconductor device can be reduced.

Furthermore, according to the semiconductor device of this Embodiment 4,the voltage for the N-type deep well regions 12 is fixed in the block ofN-type substrate bias-variable transistors 26 and the block of DTMOSs27, 28. Therefore, it becomes easier to control the latch-up phenomenon.As a result of this, the reliability of the semiconductor device isimproved.

EMBODIMENT 5

Although not shown, a CMOS circuit may also be made up by using thesemiconductor device according to any one of Embodiments 1 to 4. A CMOScircuit of low power consumption and high speed can be implemented byproperly combining respective advantages of the DTMOSs that are capableof obtaining high drive current with low voltage drive, and thesubstrate bias-variable transistors that are capable of reducing theoff-leak current to quiet a small one. Furthermore, when a plurality ofcircuit blocks of the substrate bias-variable transistors are formed andcircuit blocks other than those which should be put into the activestate are put into the standby state, the CMOS circuit can be made evenlower in power consumption.

EMBODIMENT 6

The semiconductor device according to any one of Embodiments 1 to 5 canbe used for battery-driven portable electronic devices, in particular,personal digital assistants. The portable electronic devices may beexemplified by personal digital assistants, cellular phones, gamedevices, and the like.

FIG. 9 shows a case exemplified by a cellular phone. A semiconductordevice of the present invention is incorporated into a control circuit111. It is noted that the control circuit 111 may also be formed of anLSI (Large-Scale Integrated circuit) on which logic circuits made of thesemiconductor device of the invention and memory are mixedly mounted.Reference numeral 112 denotes a battery, 113 denotes an RF(Radio-Frequency) circuit part, 114 denotes a display part, 115 denotesan antenna part, 116 denotes a signal line, and 117 denotes a powersupply line.

By applying the semiconductor device of the invention to a portableelectronic device, it becomes realizable to lower the power consumptionof the LSI part to a large extent while the functions and operatingspeed of the portable electronic device are maintained. As a result ofthis, the battery life can be prolonged to a large extent.

The semiconductor device of the present invention is a semiconductordevice including DTMOSs and substrate-bias variable transistors, inwhich deep well regions opposite in conductive type to the semiconductorsubstrate are electrically isolated.

With this arrangement, a plurality of circuit blocks of substratebias-variable transistors can be formed for each of different conductivetypes. Therefore, it becomes possible to properly divide the circuitblocks into circuit blocks that should be put into the active state andcircuit blocks that should be put into the standby state, for eitherconductive type, so that the power consumption of the semiconductordevice can be reduced.

Also, in one embodiment of the invention, the deep well regions in acircuit block composed of substrate bias-variable transistors and thedeep well regions in other device portions (a circuit block of substratebias-variable transistors of opposite conductive type and DTMOS portion)are electrically isolated from each other. Therefore, parasiticcapacitance due to the PN junction at boundaries of deep well regionscan be reduced, so that the power consumption of the semiconductordevice can be reduced. Still also, since the voltage for the deep wellregions of the DTMOS portion can be fixed, the latch-up phenomenon canbe suppressed.

Also, in the semiconductor device of one embodiment of the invention,for a case where a shallow well region located on one side of a deviceisolation region and a shallow well region on the other side aredifferent in conductive type from each other, and where a deep wellregion located on one side of the device isolation region and a deepwell region located on the other side are different in conductive typefrom each other, the width of the device isolation region is made widerthan the width of a device isolation region in which shallow wellregions located on both sides are identical in conductive type to eachother and moreover deep well regions located on both sides are identicalin conductive type to each other. Therefore, punch-throughs between wellregions and threshold shifts of devices due to dopant diffusion can besuppressed.

Also, the portable electronic device of the present invention, intowhich the above-described semiconductor device of the invention isincorporated, is capable of reducing the power consumption of the LSIpart to a large extent, thus allowing the battery life to be prolongedto a large extent.

1. A semiconductor device comprising: one first-conductive-typesemiconductor substrate; a plurality of second-conductive-type deep wellregions formed in the semiconductor substrate; a first-conductive-typedeep well region formed in the second-conductive-type deep well regions;a first first-conductive-type shallow well region formed on thefirst-conductive-type deep well region; a first second-conductive-typeshallow well region formed on the first-conductive-type deep wellregion; a second first-conductive-type shallow well region formed on thesecond-conductive-type deep well regions; a secondsecond-conductive-type shallow well region formed on thesecond-conductive-type deep well regions; a device isolation region; asecond-conductive-type field effect transistor formed on the firstfirst-conductive-type shallow well region; an input terminal which isformed on the first first-conductive-type shallow well region and whichserves for changing a substrate bias of the second-conductive-type fieldeffect transistor; a first-conductive-type field effect transistorformed on the second second-conductive-type shallow well region; aninput terminal which is formed on the second second-conductive-typeshallow well region and which serves for changing a substrate bias ofthe first-conductive-type field effect transistor; asecond-conductive-type dynamic threshold transistor which is formed onthe second first-conductive-type shallow well region and in which a gateelectrode and the second first-conductive-type shallow well region areelectrically connected to each other; and a first-conductive-typedynamic threshold transistor which is formed on the firstsecond-conductive-type shallow well region and in which a gate electrodeand the first second-conductive-type shallow well region areelectrically connected to each other, wherein the secondfirst-conductive-type shallow well region is electrically isolated fromdevice to device by the device isolation region and thesecond-conductive-type deep well regions, and the firstsecond-conductive-type shallow well region is isolated from device todevice by the device isolation region and the first-conductive-type deepwell region, wherein the plurality of second-conductive-type deep wellregions are electrically isolated at a boundary between thefirst-conductive-type field effect transistor and thesecond-conductive-type field effect transistor, at a boundary betweenthe first-conductive-type field effect transistor and thefirst-conductive-type dynamic threshold transistor, or at a boundarybetween the first-conductive-type field effect transistor and thesecond-conductive-type dynamic threshold transistor.
 2. Thesemiconductor device according to claim 1, wherein the plurality ofsecond-conductive-type deep well regions are electrically isolated bythe first-conductive-type semiconductor substrate.
 3. The semiconductordevice according to claim 1, wherein a first-conductive-type dopantregion is formed between the plurality of second-conductive-type deepwell regions, and the plurality of second-conductive-type deep wellregions are electrically isolated by the first-conductive-typesemiconductor substrate and the first-conductive-type dopant region. 4.The semiconductor device according to claim 1, wherein a deviceisolation region is formed between the plurality ofsecond-conductive-type deep well regions, and the plurality ofsecond-conductive-type deep well regions are electrically isolated bythe first-conductive-type semiconductor substrate and the deviceisolation region.
 5. The semiconductor device according to claim 1,wherein a first-conductive-type dopant region and a device isolationregion are formed between the plurality of second-conductive-type deepwell regions, and the plurality of second-conductive-type deep wellregions are electrically isolated by the first-conductive-typesemiconductor substrate, the first-conductive-type dopant region and thedevice isolation region.
 6. The semiconductor device according to claim1, wherein out of the device isolation regions, given a width A ofeither a device isolation region of which a shallow well region placedon one side and a shallow well region placed on the other side aredifferent in conductive type from each other, or a device isolationregion of which a deep well region placed on one side and a deep wellregion placed on the other side are different in conductive type fromeach other and moreover which is in contact with the deep well regionsplaced on both sides thereof, and given a width B of a device isolationregion of which a shallow well region placed on one side and a shallowwell region placed on the other side are identical in conductive type toeach other and of which a deep well region placed on one side and a deepwell region placed on the other side are identical in conductive type toeach other and which is in contact with the deep well regions placed onboth sides thereof, then A>B.
 7. The semiconductor device according toclaim 1, wherein out of the device isolation regions, given a width A ofeither a device isolation region of which a shallow well region placedon one side and a shallow well region placed on the other side aredifferent in conductive type from each other, or a device isolationregion of which a deep well region placed on one side and a deep wellregion placed on the other side are different in conductive type fromeach other and moreover which is in contact with the deep well regionsplaced on both sides thereof, then 0.18 μm<A<0.7 μm.
 8. Thesemiconductor device according to claim 1, wherein the device isolationregions are formed of STI (Shallow Trench Isolation).
 9. Thesemiconductor device according to claim 1, wherein a complementarycircuit is made up by the first-conductive-type dynamic thresholdtransistor and the second-conductive-type dynamic threshold transistor,or by the first-conductive-type field effect transistor and thesecond-conductive-type field effect transistor, or by thefirst-conductive-type dynamic threshold transistor and thesecond-conductive-type field effect transistor, or by thefirst-conductive-type field effect transistor and thesecond-conductive-type dynamic threshold transistor.
 10. A portableelectronic device which includes the semiconductor device as defined inclaim
 1. 11. A semiconductor device, comprising: onefirst-conductive-type semiconductor substrate; a plurality ofsecond-conductive-type deep well regions formed in the semiconductorsubstrate; a plurality of blocks, each block comprising one of saidsecond-conductive-type deep well regions, each of said blockscomprising: at least one first-conductive-type deep well region formedin the second-conductive-type deep well region associated with theblock, at least one second-conductive-type field effect transistor inelectrical connection to said at least one first-conductive-type deepwell region, at least one first-conductive-type field effect transistorin electrical connection to said second-conductive-type deep well regionassociated with the block, at least one first-conductive-type dynamicthreshold transistor in electrical connection to said at least onefirst-conductive-type deep well region, and at least onesecond-conductive-type dynamic threshold transistor in electricalconnection to said second-conductive-type deep well region associatedwith the block; and wherein the plurality of second-conductive-type deepwell regions are electrically isolated at a boundary between thefirst-conductive-type field effect transistor located within a block andthe second-conductive-type field effect transistor located withinanother neighboring block.
 12. A semiconductor device, comprising: onefirst-conductive-type semiconductor substrate; a plurality ofsecond-conductive-type deep well regions formed in the semiconductorsubstrate; a plurality of blocks, each block comprising one of saidsecond-conductive-type deep well regions, each of said blockscomprising: at least one first-conductive-type deep well region formedin the second-conductive-type deep well region associated with theblock, at least one second-conductive-type field effect transistor inelectrical connection to said at least one first-conductive-type deepwell region, at least one first-conductive-type field effect transistorin electrical connection to said second-conductive-type deep well regionassociated with the block, at least one first-conductive-type dynamicthreshold transistor in electrical connection to said at least onefirst-conductive-type deep well region, and at least onesecond-conductive-type dynamic threshold transistor in electricalconnection to said second-conductive-type deep well region associatedwith the block; and wherein the plurality of second-conductive-type deepwell regions are electrically isolated at a boundary between thefirst-conductive-type field effect transistor located within a block andthe first-conductive-type dynamic threshold transistor located withinanother neighboring block.
 13. A semiconductor device, comprising: onefirst-conductive-type semiconductor substrate; a plurality ofsecond-conductive-type deep well regions formed in the semiconductorsubstrate; a plurality of blocks, each block comprising one of saidsecond-conductive-type deep well regions, each of said blockscomprising: at least one first-conductive-type deep well region formedin the second-conductive-type deep well region associated with theblock, at least one second-conductive-type field effect transistor inelectrical connection to said at least one first-conductive-type deepwell region, at least one first-conductive-type field effect transistorin electrical connection to said second-conductive-type deep well regionassociated with the block, at least one first-conductive-type dynamicthreshold transistor in electrical connection to said at least onefirst-conductive-type deep well region, and at least onesecond-conductive-type dynamic threshold transistor in electricalconnection to said second-conductive-type deep well region associatedwith the block; and wherein the plurality of second-conductive-type deepwell regions are electrically isolated at a boundary between thefirst-conductive-type field effect transistor located within a block andthe second-conductive-type dynamic threshold transistor located withinanother neighboring block.